Embodiments of the present invention relate to digital circuits, and more specifically, to dynamic logic circuits.
Sub-threshold leakage currents in dynamic circuits may limit performance as process technology leads to smaller and smaller device size. To maintain circuit robustness, designers have used various approaches, but with the result that circuit delay and performance may be adversely affected. These issues are discussed in more detail by considering the prior art domino logic in FIG. 1.
The domino logic gate in FIG. 1 comprises dynamic stage 102 and static stage 104. In the particular example of FIG. 1, static stage 104 is a single-input, single-output inverter, but other inverting static logic may be employed. nMOS (Metal Oxide Semiconductor) logic 108 comprises one or more nMOSFETs (Metal Oxide Semiconductor Field Effect Transistor) to conditionally pull node 110 LOW during an evaluation phase, depending upon the input voltages at input ports 106. (Input ports 106 may actually consist of only one input port, e.g., if the domino gate is an inverter gate.)
During an evaluation phase, clock signal xcfx86 is HIGH so that pMOSFET 112 is OFF and nMOSFET 114 is ON to conditionally provide a low impedance path between node 110 and ground 128 at voltage VSS depending upon the input voltages at input ports 106. During a pre-charge phase, clock signal xcfx86 is LOW so that nMOSFET 114 is OFF and pMOSFET 112 is ON to pull node 110 HIGH by providing a low impedance path between node 110 and power rail 126 at supply voltage VCC.
If the domino gate of FIG. 1 is not at a clock boundary, then nMOSFET 114 may be removed so that nMOS logic 108 is connected directly to ground 128 if all input voltages are LOW during an evaluation phase. This is the reason for illustrating nMOSFET 114 with dashed lines. A half-keeper comprising inverter 116 and pMOSFET 118 is designed to maintain node 110 HIGH unless it is otherwise pulled LOW by nMOS logic 108 during an evaluation phase. Only one domino gate is shown in FIG. 1, but in practice, a plurality of such gates are connected together to form a larger domino circuit. For example, output port 124 of the domino logic gate may be connected to an input port of another domino logic gate.
Sub-threshold leakage current in an nMOSFET comprises source-drain current when the gate-to-source voltage VGS is less than the threshold voltage VT. Consider the circuit of FIG. 1 during an evaluation phase in which the input voltages at input ports 106 are such that nMOS logic 108 does not pull node 110 LOW. (That is, the input voltages are such that the output logic voltage at output port 124 of the domino logic gate is supposed to be LOW.) Unless the circuit of FIG. 1 is designed properly, sub-threshold leakage current through nMOS logic 108 during the evaluation stage may prevent the half-keeper from maintaining node 110 sufficiently HIGH, so that output port 124 may provide an incorrect logic level. One approach to mitigate this effect is to size the half-keeper larger so as to maintain acceptable robustness. However, a larger half-keeper may cause evaluation contention with nMOS logic 108 during an evaluation phase if nMOS logic 108 tries to pull node 110 LOW, which may increase the delay of the domino gate. Another approach is to employ high-VT (high-threshold-voltage) nMOSFETs in MOS logic 108 to reduce the amount of sub-threshold leakage current. However, using high-VT nMOSFETs in MOS logic 108 may increase the delay in the domino gate.